The invention relates to an electronic component having a semiconductor chip comprising a multi-layered coating that includes at least one interconnect layer, one insulation layer, and one planarization layer.
Planarization layers manifest problems adhering to insulation and/or interconnect layers, particularly in view of that fact that their thermal coefficient of expansion is not suited to the expansion behavior of the insulation layers and/or interconnect layers at all processing temperatures that arise in the process of manufacturing the electronic component. The danger of a detachment of the planarization layer increases in correspondence to the distance from the thermo-mechanical neutral point of the semiconductor chip, which is located in the geometric center of the surface of the active semiconductor chip given a symmetrical construction of the semiconductor structures, the structured insulation layers and the structured interconnect layers. Given an asymmetrical construction of a multi-layer coating of a semiconductor chip, the thermo-mechanical neutral point can be offset from the geometric center of the semiconductor chip. Despite this offset, the thermo-mechanical neutral point of a semiconductor chip is located in the vicinity of the geometric center of a semiconductor chip and thus in the center region. Thus, the problem regions with respect to the adhesion of the planarization layer to insulation layers are situated in the corner regions of a semiconductor chip.
It is the object of the invention to prevent the disengagement or displacement of a planarization layer from a semiconductor having a multi-layer coating.
This object is achieved with the subject matter of the independent claim. Additional advantageous developments of the invention derive from the subclaims.
According to the invention, the planarization layer comprises a glass layer having embedded adhesion regions which provide adhesion surfaces to neighboring insulation layers. These embedded adhesion regions have the advantage that they can be inserted in all problem zones of the planarization layer. Since the adhesion surfaces of the adhesion regions are fixed in relation to the adjacent insulation layers, the glass layer is prevented from sliding and lifting off at these adhesion regions, and the glass layer is fixed between the adhesion regions. To this end, the adhesion regions are applied to the semiconductor chip having a multi-layer coating prior to application of the glass layer.
In an embodiment of the invention, the glass layer consists of a glass compound that is thrown or spun on and polished on the surface which is averted from the semiconductor chip for leveling purposes. When it is thrown or spun on, the glass compound initially covers not only the adhesion regions with their adhesion surfaces for adjacent insulation layers, but also covers unevennesses of the multi-layer semiconductor chip as well as through-contacts to underlying interconnects. Polishing the surface of the glass layer erodes it sufficiently to produce a plane that comprises glass layer regions, through-contact regions, and adhesion regions, so that additional insulation layers, interconnect layers and through-contacts can be built on this plane with a high degree of precision, a completely planar surface being available again for such further processing of the semiconductor chip.
In another development of the invention, the adhesion regions consist of a metal coating. Metal coatings on insulation layers on semiconductor chips have the advantage of adhering extremely durably, so that such a metal coating on the insulation layer of a multi-layer coating of a semiconductor chip fundamentally represents an obstacle to the sliding of the glass layer of the planarization layer.
When the ultimate layer structure subsequent to the planarization layer begins with an additional insulation layer, the adhesion areas are sandwiched between lower and upper insulation layers, to which metal coatings adhere particularly well, so that the region of the planarization layer which is occupied by the glass layer is prevented from sliding or disengaging from the underlying bottom insulation layer and/or the overlying top insulation layer.
In another embodiment of the invention, the adhesion regions of the planarization layer are denser in corner regions of the semiconductor chip than in the center region of the semiconductor chip. By extension, this advantageous embodiment of the invention may provide that no adhesion regions be arranged in the center region, and that the arrangement of adhesion regions be concentrated in the corner regions, especially since the corner regions in a semiconductor chip are located furthest from the thermo-mechanical neutral point of the semiconductor chip.
The adhesion regions can have a variety of shapes. In one embodiment of the invention, the planarization layer of the semiconductor chip comprises angular strips as the adhesion regions in corner regions of the semiconductor chip. The angles can be rectangular, with the legs of the angular strips growing shorter as the strips approach the center of the semiconductor chip. The stagger, i.e. the mutual spacing between the angular strips, can also be varied so that the spacing between the angular strips increases as they approach the center. The angular strips are interrupted at the locations at which through-contacts are required for contacting through to the bottom interconnect layers.
Another embodiment of the invention provides that the planarization layer of the semiconductor chip comprise adhesion regions with rounded contours. Rounded contours represent adhesion regions that do not comprise corners, vertices or indentations, so that microtear formation is not induced in the surrounding glass layer given cyclic thermal stress. For this reason, round, i.e. circular, adhesion regions are advantageous.
The adhesion regions are produced from materials whose adhesivity on insulation layers in semiconductor technology has been proven effective. In particular, in one embodiment of the invention the adhesion regions consist of an aluminum alloy coating. Aluminum alloys having small proportions of copper and/or silicon have proven effective and adhere permanently to the insulation layers, so that in an electronic component wherein adhesion regions consisting of aluminum alloys are embedded in the planarization layer, these regions can effectively adhere both to the underlying bottom insulation layer and to the subsequent overlying top insulation layer, and can thus prevent the material of the planarization layer from lifting or sliding off at the critical adhesion locations far from the thermo-mechanical neutral point of the semiconductor chip.
Since copper alloys are being used with increasing frequency in semiconductor technology for the interconnect layers, it is expedient to produce the adhesion regions in semiconductor chips having copper interconnect layers from copper alloys, in order to remain compatible with the respective process technologies.
A further object of the present invention is to optimize and test the geometry of the adhesion regions, their position on the chip, and the materials for the adhesion regions.
This object is achieved by an electronic component having a test structure on a semiconductor chip, which structure comprises a multi-layer coating including at least one interconnect layer, one bottom insulation layer, one top insulation layer, and one intermediate planarization layer with embedded adhesion regions, and which additionally comprises at least one test through-contact in the corner regions of its planarization layer, which extends through the planarization layer and is connected above and below the planarization layer to measuring interconnects.
The test through-contact has a microscopic diameter, given which it is possible to detect minimal displacements of the planarization layer. In this context, the term xe2x80x9cmicroscopicxe2x80x9d refers to dimensions that are measurable only with a light microscope. The corner region of a semiconductor chip is used for this test through-contact in order to test the greatest stress on the planarization layer to arise in the corner region. If the planarization layer detaches from the underlying insulation layer or shifts relative thereto, the test through-contact is interrupted, and a current is no longer able to pass via the interrupted test through-contact between the measuring interconnects, which are attached on the bottom of the planarization layer and the top of the planarization layer and connected to the test through-contact. If the planarization layer is prevented from disengaging or shifting relative to the underlying insulation layer by correspondingly optimized adhesion regions, then the test through-contact remains intact, and a measuring current can flow from the bottom measuring interconnect to the top measuring interconnect on the bottom and top sides of the planarization layer, respectively.
With this test structure on the semiconductor chip of an electronic component, the construction of the adhesion regions can be checked and optimized. In order to check the measurement of current which is performed by way of the measuring interconnects and the test through-contact, the semiconductor chip comprises a first measuring contact surface on the top side of the planarization layer, which is connected to the top measuring interconnect, and a second measuring contact surface on the top side of the planarization layer, which is connected to the bottom measuring track via a measuring through-contact through the planarization layer. As a consequence, a simple method of current measurement can be utilized to provide proof as to whether the adhesion regions of a semiconductor chip having a test structure are operating effectively, or it will be necessary to correct the surface-area ratio between the adhesion region and the planarization surface, the arrangement and distribution of the adhesion regions on the semiconductor chip, or the shape and size of individual adhesion regions and the type of adhesion material.
Comparably, test through-contacts can be arranged in the center region as well as the margin regions of the semiconductor chip in order to prevent misinterpretations of an interruption of the test through-contacts, given that interruptions, which are caused by cyclic thermal stresses of the semiconductor chip, of the test through-contact in the center region, i.e. in the vicinity of the thermo-mechanical neutral point of the semiconductor chip, are an indication that the cause of the interruption is not related to the embedded adhesion regions. If interruptions of the test through-contact occur only in the margin region and not in the center region, the adhesion regions require correction. If interruptions of the test through-contact occur neither in the center region nor in the margin region, the embedded adhesion regions have achieved their object completely. A method of manufacturing electronic components having planarization layers which is carried out on this basis can therefore be based on adhesion regions with guaranteed structures, giving rise to mass production of reliable electronic components having planarization layers.
In an embodiment of the invention, each electronic component of a semiconductor wafer comprises a test through-contact in a corner region. The space consumed by such a test through-contact having measuring interconnects represents only a small space and can nevertheless guarantee when adhesion problems have occurred on the semiconductor wafer between the planarization layer and the insulation layers.
In another embodiment of the test structure of a semiconductor chip, at least one corner region of the semiconductor chip comprises angular strips as adhesion regions. With the aid of the test structure, the reliability of these angular strips as adhesion regions can be examined very precisely; specifically, the reliability of an overall wafer or of an entire batch can be statistically determined during production.
Another embodiment of the test structure of a semiconductor chip provides that at least one corner region comprise square-shaped adhesion regions. Square adhesion regions can be distributed in a corner region uniformly or in different densities and have the advantage over an angular strip structure that their distribution can be varied more widely in the corner region of a semiconductor chip.
In another embodiment of the test structure of a semiconductor chip, rounded contours are provided as adhesion regions. In the extreme case, these rounded contours are circular adhesion regions. Rectangular and square surfaces that have rounded corners are possible as well. Semiconductor structures such as these have the advantage that voltage peaks cannot develop in the planarization layer, since sharp corners are completely avoided in the structure.
In another embodiment of the invention, several metal layers are provided in the semiconductor chip, which are jointly connected to a single test through-contact and which comprise a measuring interconnect, which is connected to the test through-contact, for each of the metal layers. For each of the metal track layers, a measuring contact surface is provided on the topmost interconnect layer, these being connected to the respective test through-contact via measuring lines by way of measuring through-contacts. The adhesivity of various insulation and planarization layers relative to one another is thus testable with the aid of a single test through-contact.
A method for producing an electronic component with a semiconductor chip and a multi-layer coating comprising interconnect layers and insulation layers and at least one planarization layer including adhesion regions comprises the following steps:
a) produce a semiconductor chip with first layers of a multi-layer coating in a layer sequence of at least one interconnect layer and at least one terminating insulation layer including through-contacts to the interconnect layer;
b) deposit a metallic adhesion layer on the terminating insulation layer of the first layer;
c) structure the adhesion layer into adhesion regions and through-contact regions;
d) apply a glass layer;
e) planarize the glass layer into a planarization layer which includes embedded adhesion-layer regions and through-contact regions;
f) complete the multi-layer coating by applying additional layers, beginning with an additional insulation layer.
With a method such as this, an electrical component is produced which comprises a planarization layer that is so fixed upon the multi-layer coating by embedded adhesion regions that shifting, displacement, or disengagement of the planarization layer cannot occur in critical areas located at a distance from the neutral thermal point of the semiconductor chip. To this end, before the material of the planarization layer is applied, an adhesion layer is applied in equal or greater thickness as that of the future planarization layer and when the adhesion layer is then structured, adhesion regions of the adhesion layer having a thickness slightly greater than or equal to that of the future planarization layer remain on the preceding insulation layer. Besides the adhesion regions, a metallic extension of the through-contacts to the interconnect layers beneath and between the insulation layers must be applied and structured in the process of structuring the adhesion layer. Because the adhesivity of the metals on the insulation layer, which are common metals for interconnects in semiconductor technology, has already been proven effective, the adhesion layer is also produced from a metal of this type, so that through-contact regions can also be realized during the process of structuring the adhesion layer into adhesion regions. These through-contacts should extend from the deeper metal layers to the future surface of the planarization layer, so that access to through-contacts of the deeper interconnect layers can also be created.
Following the structuring of the adhesion layer into adhesion regions and through-contact regions, the actual material of the planarization layer, namely a glass layer, is applied. This glass layer covers not only the intervening spaces between the adhesion regions but also the adhesion regions themselves as well as the through-contact regions. Furthermore, the surface of the glass layer exactly reproduces the unevennesses which emerged in the surface of the semiconductor chip in the preceding steps and were formed in the application of the first layers of the multi-layer coating. For this reason, in a subsequent step the glass layer, along with the embedded adhesion regions and through-contacts, undergoes chemical-mechanical polishing and erosion to a uniform level, whereby all unevennesses are eliminated, with the result that the planarized surface of the planarization layer substantially comprises the material of the glass layer, the adhesion surfaces, and the through-contacts.
For testing and checking purposes, a somewhat differently constructed electronic component is produced, which comprises a test structure on a semiconductor chip. This test structure on a semiconductor chip was invented in order to be able to demonstrate the adhesivity, or the improvement of adhesion, conditioned by the adhesion regions, and to be able to detect errors in the adhesion of the planarization layer during production. To accomplish these aims, the test structures realized on the semiconductor chip are produced by the following method:
a) Produce a semiconductor chip having at least one bottom insulation layer and at least one bottom interconnect layer on the bottom insulation layer;
b) structure the bottom interconnect layer into at least one bottom measuring interconnect;
c) apply an adhesion layer;
d) structure the adhesion layer into adhesion regions, at least one test through-contact at one end of the measuring interconnect, and at least one measuring through-contact at the other end of the measuring interconnect;
e) apply a glass layer to the bottom insulation layer with the structured adhesion layer;
f) planarize the glass layer into a planarization layer including adhesion layer regions and the test through-contact and the measuring through-contact;
g) apply a top insulation layer on the planarization layer having through-contact openings to the test and measuring through-contacts;
h) apply an interconnect layer having at least one top measuring interconnect and measuring contact surfaces for top and bottom measuring interconnects.
The product of this method is an electronic component having a test structure with which it is possible not only to test the reliability performance of new adhesion layer regions embedded in a planarization plane with respect to their ability to check for disengagement or shifting of the planarization layer relative to the bottom and top insulation layers, but also to continuously monitor finished semiconductor chips having planarization layers. To this end, in this method at least one test through-contact is created in the planarization layer extending from an interconnect layer beneath the planarization layer to an interconnect layer above the planarization layer, i.e. through the entire thickness of the planarization layer. This test through-contact can be microscopic, because this itself is not intended to be furnished with pivots of a testing device. Rather, a measuring interconnect is disposed in the interconnect layer situated beneath the planarization, which is connected to the bottom end of the test through-contact and leads from there to a measuring through-contact which is connected to a measuring contact surface on the top side of the planarization layer.
The measuring contact surface which is electrically connected to the bottom end (or the beginning) of the test through-contact, by way of the measuring through-contact and a bottom measuring interconnect, can be constructed large enough that either continuing measuring wires can be installed on this measuring contact surface, or pivots of a corresponding testing device can be installed. The top end of the test through-contact, which is microscopic just as the test through-contact itself, is connected to a measuring interconnect on the top surface of the planarization layer or on the surface of the top insulation layer, while the free end of the measuring interconnect flows into a measuring contact surface on which a second pivot of a testing device can be installed or a measuring wire can be attached. Upon completion of the steps for producing a test structure on a semiconductor chip and possible thermo-test cycles, it can be determined between the two measuring contact surfaces or the attached measuring wires whether or not the test through-contact has been interrupted by the thermal treatment owing to displacement of the planarization layer relative to the top or bottom insulation layer.
One alternative for executing the method, the adhesion layer is applied by a sputter method. To this end, a source material consisting of the material of the adhesion layer is sputtered in a vacuum apparatus and simultaneously applied to the insulation layer that underlies the planarization layer. The source material consists of a metal alloy which is provided for the adhesion regions and which can correspond to the metal alloy for the interconnect layers.
Another development for executing the method provides that the adhesion layer be applied by evaporation. Here, the source material for the adhesive material of the adhesion regions is liquefied in a cup or vessel and vaporized onto the surface of the insulation layer underlying the future planarization layer.
The adhesion layer can also be applied by the decomposition of metalorganic substances in a vapor phase deposition method. Here, a metalorganic substance is converted into the vapor phase and guided over the insulation layer that underlies the future planarization layer, whereby the metal of the metalorganic compound settles on the insulation layer from the vapor phase.
Because in these methods for applying the adhesion layer the whole area of the bottom insulation layer is covered with a metal alloy, this must be structured into adhesion regions and through-contact regions in a subsequent step. The through-contact regions provide for electrical connections through the planarization layer to the bottom interconnect layers, whereas the adhesion regions themselves should be embedded within the planarization layer and between the bottom and top insulation layers in a fully insulated fashion.
In a development for executing the method, this type of structuring of the adhesion layer can be accomplished by a masking method using a photolithography technique. Upon the application of a structured mask to the adhesion layer using this technique, the regions in which an embedded layer is to be applied are dry-etched away by a plasma etching method or are alternatively removed by a wet chemical method. Next, the adhesion regions and the through-contact regions on the bottom insulation layer are covered by the adhesion layer, and a glass layer can be applied to the surface so as to cover the whole surface, including the adhesion layer regions and the through-contact regions.
The glass layer can be applied by a throwing or spraying method with a subsequent drying process. The advantage of these methods is that they make it possible to produce an arbitrarily thick glass layer on the bottom insulation layer.
The glass layer can also be applied by the sputter method or by deposition from a plasma. These methods are distinguished by the extreme purity of the applied layers, since both methods are executed in a vacuum. Another possibility for carrying out the method is to apply the glass layer by chemical vapor-phase deposition.
Once the glass layer has been applied, all unevennesses of the underlying surface of the semiconductor and the multi-layer coating are reproduced on the top surface of the glass layer. Therefore, these unevennesses are eroded in a chemical-mechanical method, forming a planarization layer. This planarization layer makes it possible to build subsequent layers based on a wholly planar surface. First, an additional insulation layer is applied, which comprises a very good bond to the adhesion regions and in which through-openings are installed at the locations at which the through-contacts to the bottom interconnect structures are disposed. These through-contacts can be connected to one another by way of a metallic interconnect structure on the insulation layer or can be led to contact surfaces of the semiconductor chip. Lastly, a passivation layer is placed on this structure, which is intended to protect the interconnects and which comprises openings only at locations at which contact surfaces of the semiconductor chip are provided.